Verilog & VHDL

Verilog & VHDL

VHDL is suited to the specification, design and description of digital electronic hardware. VHDL is not ideally suited for abstract system-level simulation, prior to the hardware-software split. Simulation at this level is usually stochastic, and is concerned with modelling performance, throughput, queueing and statistical distributions. VHDL has been used in this area with some success, but is best suited to functional and not stochastic simulation. VHDL is suitable for use today in the digital hardware design process, from specification through high-level functional simulation, manual design and logic synthesis down to gate-level simulation. VHDL tools usually provide an integrated design environment in this area. VHDL is not suited for specialized implementation-level design verification tools such as analog simulation, switch level simulation and worst case timing simulation. VHDL can be used to simulate gate level fanout loading effects providing coding styles are adhered to and delay calculation tools are available. The standardization effort named VITAL (VHDL Initiative Toward ASIC Libraries) is active in this area, and is now bearing fruit in that simulation vendors have built-in VITAL support.

Verilog can be used at different levels of abstraction . Verilog restricts the designer to working with pre-defined system functions and tasks for stochastic simulation and can be used for modelling performance, throughput and queueing but only in so far as those built-in langauge features allow. Designers occasionally use the stochastic level of abstraction for this phase of the design process. Verilog is suitable for use today in the digital hardware design process, from functional simulation, manual design and logic synthesis down to gate-level simulation. Verilog tools provide an integrated design environment in this area. Verilog is also suited for specialized implementation-level design verification tools such as fault simulation, switch level simulation and worst case timing simulation. Verilog can be used to simulate gate level fanout loading effects and routing delays through the import of SDF files.